`timescale 1ns / 1ps
module ALU(OP, A, B, F, ZF, CF, OF, SF, PF);
parameter size=32;
     input [3:0]OP;
     input [size:1]A;
     input [size:1]B;
    output [size:1]F;
    output ZF,CF,OF,SF,PF;
    reg [size:1]F;
    reg C,ZF,CF,OF,SF,PF;
    always @(*)begin
        C=0;
        case(OP)
            4'b0000:begin F=A&B;end
            4'b0001:begin F=A|B;end
            4'b0010:begin F=A^B;end
            4'b0011:begin F=~(A|B);end
            4'b0100:begin {C,F}=A+B;end
            4'b0101:begin {C,F}=A-B;end
            4'b0110:begin F=A<B;end
            4'b0111:begin F=B<<A;end   
        endcase
        ZF=(F==0);
        CF=C;
        OF=A[size]^B[size]^F[size]^C;
        SF=F[size];
        PF=~^F;
        end
endmodule
